Paper Title :Memory Based Floating Point FFT Processor using Memory Block Vector
Author :S. Butchi Babu, T. Naga Mounika, Hemasri Chundi
Article Citation :S. Butchi Babu ,T. Naga Mounika ,Hemasri Chundi ,
(2018 ) " Memory Based Floating Point FFT Processor using Memory Block Vector " ,
International Journal of Electrical, Electronics and Data Communication (IJEEDC) ,
pp. 10-13,
Volume-6,Issue-10
Abstract : A hypothesized conflict-free address scheme which is efficient for arbitrary point memory-based fast Fourier
transform (FFT) processor was exhibited in this paper. In the proposed scheme, a high radix decomposition method was
utilized for reducing the levels of computation and small radix connected multipath-delay-commutator butterfly units were
adopted to eliminate the complexity of the computation engine as well. Several important functions of memory-based FFT
processor were combined together, including the continuous-flow mode, variable computation size and conflict-free address
scheme. Moreover, a prime factor algorithm was employed to decrease the multiplications and the twiddle factor storage
when there subsist prime factors in the decomposition. At last, a unified Winograd Fourier transform algorithm (WFTA)
butterfly core was designed for the small 2, 3, 4, 5 point DFTs to reduce the computation complexity further.
Keywords - Conflict-free address scheme, long-term evolution (LTE), memory-based fast Fourier transform (FFT)
processor, prime factor algorithm (PFA), Winograd algorithm.
Type : Research paper
Published : Volume-6,Issue-10
DOIONLINE NO - IJEEDC-IRAJ-DOIONLINE-13978
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Copyright: © Institute of Research and Journals
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Published on 2018-12-29 |
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